In brief
An H100 GPU is not born in a single country. Its design is Californian, its fabrication Taiwanese, its assembly again Taiwanese, its memory Korean, its lithography machines Dutch. The chain that produces the chips powering AI models is geographically concentrated, technically fragile, and difficult to replicate. Understanding this chain means understanding why “ordering 10,000 GPUs” is not enough to guarantee delivery.
A chain divided into layers
Semiconductor production does not resemble an automotive assembly line. It is fragmented into distinct specialties, each dominated by a small number of players.
Chip designers (fabless) — Nvidia, AMD, Apple, Qualcomm — design chips without owning factories. They produce nanometer-level blueprints that specialized software (EDA) translates into manufacturing instructions.
Foundries manufacture these chips to order. TSMC, Samsung Foundry, and Intel Foundry are the principal players. They do not invent the chips: they etch them into silicon according to the blueprints provided.
Equipment makers produce the machines without which no foundry can operate. ASML (Netherlands) holds a unique position: it is the world’s sole manufacturer of EUV lithography machines, indispensable for the finest nodes.
Materials suppliers complete the chain: ultrapure silicon, specialty gases, photoresists — often produced by Japanese companies.
The manufacturing node: measuring fineness
A “node” refers to the fineness of transistor etching. The smaller the number, the denser and more efficient the transistors. TSMC’s N4 (approximately 4 nm) is used for Nvidia’s H100 GPUs. N3 (3 nm) equips recent Apple chips. N2 (2 nm) has been in production since 2025.
This figure is not merely a performance indicator — it is a barrier to entry. Mastering a new node takes years and costs tens of billions. TSMC produces approximately 90% of the most advanced chips (below 7 nm) worldwide, according to the SIA 2023 report. Taiwan concentrates approximately 63% of global capacity on these nodes.
In short: “4 nm” does not literally refer to transistor size — it has become a marketing name for a level of fineness. The important point: each generation requires 5 to 10 years of R&D and tens of billions of investment, so only 3 to 4 companies in the world can still run this race.
ASML: the quiet monopoly
To etch patterns at a few nanometers, foundries use EUV (Extreme Ultraviolet) lithography. These machines project light at a 13.5 nm wavelength to print minuscule circuits into silicon.
ASML is the world’s sole manufacturer of this equipment. A standard EUV machine costs between 150 and 200 million euros. The next generation — High-NA EUV (model EXE:5000) — reaches 380 million euros per unit. These machines contain more than 100,000 components, manufactured by approximately 800 subcontractors. Their short-term duplication is virtually impossible.
ASML delivered its first High-NA machines to Intel and TSMC in 2024. This new monopoly conditions the production of sub-2 nm nodes for the next decade.
CoWoS: when packaging becomes the bottleneck
A less visible aspect of the chain created the worst GPU shortages in 2023: advanced packaging.
An H100 GPU is not a single chip. It is an assembly: the main die (etched in N4 at TSMC), to which HBM3E memory (High Bandwidth Memory, produced by SK Hynix in South Korea) is bonded. This 2.5D bonding is called CoWoS (Chip-on-Wafer-on-Substrate). It takes place in specialized factories — still predominantly at TSMC.
In 2023, Nvidia could etch enough H100 dies. The problem lay elsewhere: insufficient CoWoS capacity to assemble them. Delivery lead times reached 12 to 18 months. TSMC has since invested heavily to triple this capacity, but scaling up is slow: CoWoS requires dedicated equipment and specific know-how.
In short: the 2023 GPU shortage was not a chip etching shortage. It was a packaging shortage — the step that bonds the main die and HBM memory. You could have 100,000 H100 dies ready and not be able to ship them because there were not enough CoWoS lines to assemble them.
In 2024–2025, a second bottleneck emerged: HBM3E memory. SK Hynix holds more than 50% of the market, Samsung 35%, Micron 15%. HBM production capacity is constrained by complex manufacturing processes that do not accelerate easily.
Geopolitics: when maps matter as much as patents
This geographic concentration has an obvious strategic dimension. The 2021 BCG/SIA report estimated that a total disruption of Taiwan’s supply would cost several trillion dollars and trigger a collapse of global electronics production within 6 to 12 months.
This vulnerability has triggered massive political responses.
The CHIPS and Science Act (August 2022, $52.7 billion) funds TSMC fabs in Phoenix (Arizona), Samsung in Taylor (Texas), and Intel in Ohio. First advanced-node production in the United States is expected between 2025 and 2027. But these fabs produce N4, not N3 — two to three years behind Taiwanese sites.
The EU Chips Act (€43 billion) targets 20% of global production by 2030, an objective most industry analysts consider highly ambitious.
Japan subsidized a TSMC fab in Kumamoto, operational in 2024 on mature nodes (N12/N16), and is negotiating a second fab for more advanced nodes.
Against this backdrop, US export controls (2022–2024) have banned ASML from delivering EUV machines to China, and restricted equipment from Applied Materials, Lam Research, and KLA. China continues catching up on mature nodes (28 nm and above), but remains blocked on advanced nodes.
What subsidies cannot buy
Building a fab costs $5 to $7 billion and takes several years. Making it productive is another matter entirely.
TSMC’s real advantage lies not in its machines — which others can purchase — but in its production yield: the percentage of functional chips exiting a batch. This know-how accumulates over decades. A new fab with the same ASML equipment will achieve significantly lower yields for 3 to 5 years.
Talent is the other constraint. TSMC encountered difficulties recruiting enough Taiwanese engineers for its US sites, which delayed production timelines. Human know-how transfers more slowly than concrete.
| Link in the chain | Concentration | Estimated time to duplicate | Sovereignty lever |
|---|---|---|---|
| Design (fabless) | United States (~70%) | 5-10 years | Subsidise European designers (little short-term effect) |
| Advanced foundries (≤ 7 nm) | Taiwan (~63%), Korea (~25%) | 5-7 years | US CHIPS Act, EU Chips Act — yields still far from Taiwan’s |
| EUV lithography | ASML (Netherlands, monopoly) | 10+ years | No credible substitute before 2035 |
| HBM memory | Korea (SK Hynix + Samsung ~85%) | 3-5 years | Micron is investing, but HBM yields take long to acquire |
| Advanced packaging (CoWoS) | TSMC dominant | 2-3 years | TSMC is tripling capacity, after the 2024-2025 backlog |
| Materials (silicon, gases, photoresists) | Japan dominant | 5-10 years | Slow diversification, a specific fragility |
Key takeaways
- Production of the most advanced AI chips is 90% concentrated in Taiwan and South Korea, with key equipment produced in the Netherlands.
- ASML holds an absolute monopoly on EUV and High-NA EUV lithography, indispensable for sub-3 nm nodes.
- The 2023–2024 GPU shortages were not caused by a lack of etching capacity, but by a bottleneck in advanced packaging (CoWoS) — a distinct step in the chain.
- HBM3E memory is a second bottleneck, dominated by SK Hynix, which conditions AI GPU performance.
- The US and European CHIPS Acts seek to diversify this chain, but production yield and human capital represent barriers that subsidies cannot overcome in the short term.